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Description

<h1>Verilog To Routing</h1>

The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA architecture and CAD research.

Open source CAD tools enable the investigation of new FPGA architectures and CAD algorithms, which are not possible with closed-source tools.

The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. It then performs:

Elaboration & Synthesis (ODIN II) Logic Optimization & Technology Mapping (ABC) Packing, Placement, Routing & Timing Analysis (VPR)

to produce FPGA speed and area results.

VTR is flexible and can target a wide range of hypothetical and commercial-like FPGA architectures, and includes benchmark designs suitable for evaluating FPGA architectures.

For [more information see the documentation](https://docs.verilogtorouting.org/en/latest/).

Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing.git

Project Slug

vtr-verilog-to-routing

Last Built

11 months ago failed

Maintainers

Home Page

https://verilogtorouting.org/

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Tags

verilog, fpga

Project Privacy Level

Public

Short URLs

vtr-verilog-to-routing.readthedocs.io
vtr-verilog-to-routing.rtfd.io

Default Version

latest

'latest' Version

master