Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing

Project Slug

vtr-docs

Last Built

1 year, 1 month ago failed

Maintainers

Badge

Tags

routing, synthesis, verilog, fpga, cad, eda, vpr, vtr, placement

Short URLs

vtr-docs.readthedocs.io
vtr-docs.rtfd.io

Default Version

latest

'latest' Version

master