Versions

Description

Sintel is a simulator and modeler of basic digital systems that allows, in addition to visualizing inputs and outputs in real time, to export the circuit to a hardware description language such as VHDL and verilog.

Repository

https://gitlab.com/WilferCiro/sintel.git

Project Slug

sintel

Last Built

2 years, 10 months ago passed

Maintainers

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Tags

digital-systems, modeler, simulator, verilog, vhdl

Short URLs

sintel.readthedocs.io
sintel.rtfd.io

Default Version

latest

'latest' Version

master