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Description
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。
Repository
https://github.com/Multimedia-Processing/Digital-Logic-Design
Project Slug
digital-logic-design
Last Built
6 months, 2 weeks ago failed
Maintainers
Home Page
https://gitlab.com/Multimedia-Processing/Digital-Logic-Design
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Short URLs
digital-logic-design.readthedocs.io
digital-logic-design.rtfd.io
Default Version
latest
'latest' Version
master
