vtr

Versions

Description

The Verilog-to-Routing (VTR) project. An open-source CAD system for FPGA Architecture and CAD research.

Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing.git

Project Slug

vtr

Last Built

3 hours, 18 minutes ago passed

Maintainers

Home Page

https://verilogtorouting.org

Badge

Tags

EDA, CAD, FPGA, VTR, VPR

Project Privacy Level

Public

Short URLs

vtr.readthedocs.io
vtr.rtfd.io

Default Version

latest

'latest' Version

master