vtr

Versions

Description

The Verilog-to-Routing (VTR) project. An open-source CAD system for FPGA Architecture and CAD research.

Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing.git

Last Built

1 week ago passed

Owners

Home Page

https://verilogtorouting.org

Badge

Tags

VPR, FPGA, VTR, CAD

Project Privacy Level

Public

Short URLs

vtr.readthedocs.io
vtr.rtfd.io

Default Version

latest

'latest' Version

master