Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing

Project Slug

vtr-docs

Last Built

4 years, 7 months ago failed

Maintainers

Badge

Tags

cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr

Short URLs

vtr-docs.readthedocs.io
vtr-docs.rtfd.io

Default Version

latest

'latest' Version

master