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Description
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Repository
https://github.com/SystemRDL/PeakRDL-regblock.git
Project Slug
peakrdl-regblock
Last Built
2 weeks, 4 days ago passed
Maintainers
Home Page
https://github.com/SystemRDL/PeakRDL-regblock
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Short URLs
peakrdl-regblock.readthedocs.io
peakrdl-regblock.rtfd.io
Default Version
latest
'latest' Version
main
