Versions
Description
The Verilog-to-Routing (VTR) project. An open-source CAD system for FPGA Architecture and CAD research.
Repository
https://github.com/verilog-to-routing/vtr-verilog-to-routing.git
Project Slug
vtr
Last Built
8 hours, 27 minutes ago passed
Maintainers
Home Page
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Tags
Short URLs
vtr.readthedocs.io
vtr.rtfd.io
Default Version
latest
'latest' Version
master