vtr

Versions

Description

The Verilog-to-Routing (VTR) project. An open-source CAD system for FPGA Architecture and CAD research.

Repository

https://github.com/verilog-to-routing/vtr-verilog-to-routing.git

Last Built

4 days, 10 hours ago passed

Maintainers

Home Page

https://verilogtorouting.org

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Tags

VPR, FPGA, EDA, VTR, CAD

Project Privacy Level

Public

Short URLs

vtr.readthedocs.io
vtr.rtfd.io

Default Version

latest

'latest' Version

master