Go to the documentation of this file. 48 #define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456)) 51 #define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183)) 53 #define RADIO_DELAY_BEFORE_DETECT 0 56 #define TSCH_CONF_HW_FRAME_FILTERING 0 58 #define PLATFORM_HAS_LEDS 1 59 #define PLATFORM_HAS_BUTTON 1 60 #define PLATFORM_HAS_LIGHT 1 61 #define PLATFORM_HAS_BATTERY 1 62 #define PLATFORM_HAS_SHT11 1 63 #define PLATFORM_HAS_RADIO 1 66 #define F_CPU 3900000uL 69 #define NETSTACK_CONF_RADIO cc2420_driver 72 #define LEDS_PxDIR P5DIR 73 #define LEDS_PxOUT P5OUT 74 #define LEDS_CONF_RED 0x10 75 #define LEDS_CONF_GREEN 0x20 76 #define LEDS_CONF_YELLOW 0x40 78 #define LEDS_CONF_LEGACY_API 1 81 #ifndef DCOSYNCH_CONF_ENABLED 82 #define DCOSYNCH_CONF_ENABLED (!(MAC_CONF_WITH_TSCH)) 86 #ifndef CC2420_CONF_SFD_TIMESTAMPS 87 #define CC2420_CONF_SFD_TIMESTAMPS (MAC_CONF_WITH_TSCH) 90 #ifndef DCOSYNCH_CONF_PERIOD 91 #define DCOSYNCH_CONF_PERIOD 30 94 #define ROM_ERASE_UNIT_SIZE 512 95 #define XMEM_ERASE_UNIT_SIZE (64*1024L) 98 #define CFS_CONF_OFFSET_TYPE long 102 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE) 105 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE) 107 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE) 108 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE) 110 #define CFS_RAM_CONF_SIZE 4096 117 #define SPI_TXBUF U0TXBUF 118 #define SPI_RXBUF U0RXBUF 121 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0) 123 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0) 125 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0) 141 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) ) 142 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) ) 144 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) ) 145 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) ) 151 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800 154 #define CC2420_FIFOP_PORT(type) P1##type 155 #define CC2420_FIFOP_PIN 0 157 #define CC2420_FIFO_PORT(type) P1##type 158 #define CC2420_FIFO_PIN 3 160 #define CC2420_CCA_PORT(type) P1##type 161 #define CC2420_CCA_PIN 4 163 #define CC2420_SFD_PORT(type) P4##type 164 #define CC2420_SFD_PIN 1 166 #define CC2420_CSN_PORT(type) P4##type 167 #define CC2420_CSN_PIN 2 169 #define CC2420_VREG_PORT(type) P4##type 170 #define CC2420_VREG_PIN 5 172 #define CC2420_RESET_PORT(type) P4##type 173 #define CC2420_RESET_PIN 6 175 #define CC2420_IRQ_VECTOR PORT1_VECTOR 178 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN))) 179 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN))) 180 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN))) 181 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN))) 184 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN)) 185 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN)) 188 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN)) 189 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN)) 192 #define CC2420_FIFOP_INT_INIT() do { \ 193 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \ 194 CC2420_CLEAR_FIFOP_INT(); \ 198 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0) 199 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0) 200 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0) 208 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN)) 210 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN)) 211 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN)) 214 #define STACK_CONF_ORIGIN ((void *)0x3900)